Operating ICs under ultra low currents and low power supplies, in complementary metal-oxide semiconductor (CMOS) technology, pose serious challenges in the design of integrated circuits. Low operating currents cause lower speeds and lower gain and higher noise in an IC. Also, rail-to-rail operations for ICs becomes a necessity given that signal-to-noise requirements at low power supplies demand input and output terminals of ICs to get as close as possible to the power supplies.